1. Field of the Invention
The present invention is in the field of digital circuits, and, more particularly, is in the field of synchronization circuits for synchronizing the transfer of data between two asynchronous digital circuits.
2. Description of the Related Art
Digital circuits in an electronic system, such as, for example, a computer system, are typically controlled by a common clock signal or by a plurality of clock signals derived from a common clock signal. Thus, the circuits are "synchronized" with respect to each other so that a signal generated by a first circuit in the system can be received by and clocked into other circuits in the system because the signals generated by the first circuit have a known phase relationship with respect to the common system clock signals. The known phase relationships typically do not exist for circuits that are controlled by independent clock signals. For example, peripheral components of a computer system often use independent clocks so that the peripheral component operates at a known frequency irrespective of the operating frequency of a computer system to which it is interconnected. Although the clock signals of a peripheral component and a computer system may have the same or similar frequencies, even very small differences in the clock frequencies cause the phase relationships between the clock signals to vary. Thus, the independent clock signals are "asynchronous" with respect to each other. Therefore, if a signal is generated by a circuit controlled by a clock which is asynchronous with the system clock of a computer system, the signal cannot be simply provided to the circuits of the computer system and clocked by the clock signals derived from the system clock. Rather, the signal must be synchronized to the system clock before the signal can be applied to the circuits of the computer system.
One particular aspect of communications between two asynchronous circuits is the transfer of data values between the two circuits. This becomes a particularly difficult problem when the two circuits operate at significantly different data rates such that one circuit can transmit data at a substantially faster data rate than the other circuit can receive it or vice versa. The data can be transferred one unit of data at a time (i.e., on a byte-by-byte basis or on a multiple byte basis wherein the multiple bytes comprise a unit of data such as a word or a double word) such that one circuit places the unit of data on a transmission bus; sets an indicator that informs the other circuit that the unit of data is ready; waits until the other circuit receives the unit of data and acknowledges receipt; clears the data ready indicator; places the next unit of data on the transmission bus; and then sets the indicator that the next unit of data is ready. Although such a system works for many systems, it is not an efficient method for transferring large amounts of data, particularly when the receiving circuit may not be ready to receive the data when the transmitting circuit is ready to send the data.
One solution to the foregoing problem is the use of a multiple data unit buffer. Such a buffer is often referred to as a FIFO (first-in/first-out) buffer. The transmitting circuit stores units of data in a plurality of storage locations within the FIFO buffer whenever the data units become available within the transmitting circuit. An input address signal selects the storage location within the FIFO buffer and a write enable signal causes the FIFO buffer to store a data unit at the selected storage unit. The input address signal and the write enable signal are synchronized to the digital clock signal within the transmitting circuit. Similarly, the receiving circuit reads units of data from the FIFO buffer whenever the receiving circuit is ready to process the data units. The receiving circuit selects a storage location to read by applying an address to the FIFO buffer in synchronism with the digital clock signal within the receiving circuit. Thus, the data units output from the FIFO buffer change at known times with respect to the clock signal in the receiving circuit.
FIFO buffers are frequently referred to as circular buffers. That is, the transmitting circuit increments a write address counter each time it stores a data unit in a storage location in the FIFO buffer. The write address counter has a maximum count value which usually corresponds to the number of storage locations in the FIFO buffer. For example, if the FIFO buffer comprises 256 storage locations, the write address counter counts from 0 to 255, wherein a count of zero addresses the first storage location in the FIFO buffer and a count of 255 addresses the 256th storage location in the FIFO buffer. Typically, the write address counter is a modulo counter. That is, when the write address counter reaches its maximum count value (e.g., 255 in this example), the next count value is the minimum count (e.g., 0). Thus, the next address location into which a data unit will be stored following the storage of a data unit in the maximum address location is the minimum address location. As discussed above, the write address counter is advanced in synchronism with the clock signal of the transmitting circuit.
The receiving circuit maintains its own read address counter which is typically similar to the write address counter and which counts from the lowest address location to the maximum address location and then starts again from the lowest address location. The read address counter is incremented in synchronism with the clock signal in the receiving circuit.
Without going into details unnecessary for the understanding of the present invention, the transmitting circuit includes a FIFO buffer write control circuit which compares the current value of the write address counter with the current value of the read address counter to determine whether data can be written into the write address location corresponding to the current value of the write counter without writing over previously written data that has not yet been read by the receiving circuit. Similarly, the receiving circuit includes a FIFO buffer read control circuit which compares the current value of the write address counter with the current value of the read address counter to determine whether the next address location to be read has been written since the last time the address location was read. Briefly, the read address counter trails the write address counter, and neither address counter is allowed to count beyond the count value in the other counter.
In order for the FIFO buffer write control circuit in the transmitting circuit and the FIFO buffer read control circuit in the receiving circuit to operate properly, it is important that the write address counter be stable when read by the read address control circuit and that the read address counter be stable when read by the write address control circuit. Because the write address counter is changed in synchronism with the transmitting circuit clock and because the read address counter is changed in synchronism with the receiving circuit clock, neither counter can be read by the other circuit without synchronization. Thus, it is necessary to synchronize the output of the write address counter to the receiving circuit clock so that the count value of the write address counter is stable when read by the FIFO read control circuit, and it is also necessary to synchronize the output of the read address counter to the transmitting circuit clock so that the count value of the read address counter is stable when read by the FIFO write address control circuit.